module t_Registers;

    reg reset,ena,enb,enc;
    reg [4:0] addra,addrb,addrc;
    reg [31:0] datac;

    wire [31:0] dataa,datab;

    Registers Reg1(reset,ena,addra,dataa,enb,addrb,datab,enc,addrc,datac);

    reg [0:5] i;
    initial 
        begin
            reset = 0;
            reset = 1;
            reset = 0;

            ena = 1;

            for(i=0;i<32;i=i+1) begin
                datac = i;
                enc = 1;
                addrc = i;

                addra = i;
                $display("Memory %d = %d.",i,dataa[0]);
            end
        end
endmodule    
